1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly, to a NAND flash memory in which the RD of a bad column is repaired by using a BIST (built in self test) function.
2. Description of the Related Art
At present, in a NAND flash memory, a bad column can be repaired by use of a redundancy cell array by using the BIST function (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-269997). As a result, the simultaneous measurement can be performed for a large number of devices, the test time consumed by the measurement can be reduced and the test cost can be lowered.
However, when a bit line (BL) at the end of the column becomes bad, it is necessary to perform the RD repair process of the adjacent column on the bad bit line side according to an instruction manual. This is because a bit line which lies at the end of the column and is open gives a bad influence on the sense operation at the read time for the adjacent column. Therefore, at present, whether the bit line at the end of the column is open or not is checked according to an input/output (I/O) signal of a tester. If the bit line at the end of the column is open, an adjacent column on the side of the bit line which is open is repaired by use of a redundancy cell array according to an instruction manual by using a tester. If this method is used, it becomes impossible to simultaneously measure a large number of devices and it becomes necessary to use a high-performance tester, and therefore, there occurs a problem that the test time is lengthened and the test cost is raised.